MOSFET fabricated on silicon on insulator (SOI) substrate provides an advantage for high speed and low power applications because of the low parasitic capacitance and the low body effect present in SOI structures. As CMOS IC technology enters the sub-50 nm range, the silicon channel and the buried oxide thicknesses must be less than 50 nm and 100 nm, respectively, in order to prevent the short channel effect (SCE), as described by R. Koh in Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 um SOI-MOSFET Jpn. J. Appl. Phys., Vol. 38, P. 2294 (1999); and R. Chau et al., A 50 nm Depleted-Substrate CMOS Transistor, IEDM, p. 621, 2001.
Many techniques have been used for SOI wafer fabrication. Among them, Separation by implaritation of oxygen (SIMOX) and SmartCut™ are considered to be the most promising for high density CMOS ICs. For CMOS technology in the sub-50 nm realm, the silicon channel and the buried oxide thicknesses need to be much less than 50 nm and 100 nm, respectively, in order to prevent the short channel effect (SCE). A super SOI, having a silicon film thickness of five nanometers and a buried oxide thickness of 20 nm might be capable of suppressing the SCE at the CMOS down-scale limit of 20 nm channel length, however, the requirements for the exceptionally thin silicon and buried oxide films exceed present manufacturing capabilities for SOI wafers.
To further improve the device performance, the buried oxide may be replaced with an insulator having a lower dielectric constant. The lowest dielectric constant for the insulator is “1,” meaning that an air gap is present under the silicon layer, which leads to the nomenclature of silicon-on-nothing (SON). SON device simulation for theoretical devices demonstrates an improved performance over SOI devices with buried oxide, having a dielectric constant of 3.9. See R. Koh, supra.
Various SON device fabrication processes have been proposed wherein the source and drains regions are connected to the substrate. Although such devices demonstrate improved performance, the structure of such devices may lead to higher parasitic source and drain capacitances, and pose a potential concern regarding subsurface puchthrough. See M. Jurczak et al., SON (Silicon on Nothing)—A New Device Architecture for the ULSI Era, VLSI Tech. Dig., p. 29, 1999; M. Jurczak, et al., Silicon-on-Nothing (SON)—an innovative Process for Advanced CMOS, IEEE Trans. El. Dev. Vol. 47, pp2179–2187 (2000); and T. Sato et al., SON (Silicon on Nothing) MOSFET Using ESS (Empty Space in Silicon) Technique for SoC Application, IEDM, p. 809, 2001.
FIG. 1 depicts a prior art SON device, generally at 10, formed on a substrate 12, which includes a gate electrode 14, a gate dielectric 16, a source 18, and a drain 20, which extend through the device channel, and a source extension 18a and a drain extension 20a. Device 10 is isolated by trench isolation 22 and is ‘floated’ on an air gap 24. However, air gap 24 is limited to the device channel 26, source extension 18a and drain extension 20a. Source 18 and drain 20 are still connected to substrate 12. FIG. 2 depicts a top plan view of device 10.